This patent application claims priority based on a Japanese patent application, H10-277151 filed on Sep. 30, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an electric part test system that tests a plurality of electric parts in parallel, and more particularly, to an electric component test system which tests a plurality of semiconductor memories in parallel.
2. Description of the Related Art
In FIG. 1, a conventional memory test system is shown as an example of an electric part test system. This memory test system comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. Each memory test unit 90 has a memory tester 50 which tests a plurality of the memory devices 52 to 56, RMEMs 32 to 36 that receive and store the test results of the memory devices 52 to 56 respectively, RCPUs 42 to 46 that are local processors and write the test results to the corresponding RMEMs 32 to 36 respectively, a VME bus which connects RCPUs 42 to 46, and an VME I/F 80 which connects the VME bus to the common memory unit 12.
The common memory unit 12 has a plurality of common memories (SMEM) 16A, 16B, . . . , that are assigned to the respective memory test units 90, and a host computer interface (EWS I/F) 20 which connects the common memories 16A, 16B, . . . , and the host computer (EWS) 10. RCPUs 42 to 46 write the test results to SMEM 16, which are read from RMEM 32 to 36 respectively. The EWS 10 reads the test results, which are stored in SMEM 16, via the EWS I/F 20.
Any one of RCPUs 42 to 46 may become a bus master of the VME bus and write the test results to SMEM 16 so that a bus arbitration occurs on the VME bus. As a result, the data transfer is delayed for the bus arbitration. When the EWS 10 notifies a command to RCPUs 42 to 46, the EWS 10 must write the command for all RCPUs 42 to 46 to SMEMs 16 respectively which is time consuming. When RCPUs 42 to 46 notify the EWS 10 of responses to the command, they are required to become bus masters in order to write the responses to SMEM 16. This bus arbitration takes long time. Furthermore, even in the case where the responses of RCPUs 42 to 46 to the command provided from the EWS 10 are the same, the EWS 10 has to read each of the responses from SMEMs 16 and is overloaded.
It is therefore an object of the present invention to provide an electric part test system which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, an electric part test system for testing a plurality of electric parts comprises a host computer which evaluates test results of the electric parts which are tested by the electric part test system; a plurality of slave processors which are controlled by the host computer and notify it of the test results of the electric parts; common memories which the slave processors may write data to and the host computer may read the data from; and a notifying unit for notifying the host computer in a case where all of the processors generate interrupt signals.
A plurality of continuous memory spaces in the common memories may be assigned to the respective slave processors. The electric part test system may further comprise local processors, one of each provided for each of the electric parts in order to receive each of the test results of the electric parts. The slave processors receive the test results from the local processors and write the test results to the common memories. Each of the slave processors receives the test results from the local processors and stores these test results in the common memory.
Each of the slave processors is connected to a respective common bus, to which a plurality of the local processors are connected. The local processors have local memories to which respective memory spaces on the bus are assigned. The memory spaces of a plurality of the local memories are continuous on the bus. When the electric part test system is initialized, each of the local processors has a means for notifying the slave processor of completion of initializing when each of the local processors initializes the local memory. The slave processor generates an interrupt signal when notified of the completion of initializing from all of the local processors that are connected to the slave processor by the bus. The host computer reads status information showing status at the time of completion of initialization when all of the slave processors generate the interrupt signals.
When the host computer sends a command to the local processors, the host computer writes the command to the common memories. The slave processors transfer the command from the common memories to the local processors.
When the local processors provided for each of the slave processors complete predetermined jobs, the slave processor notifies the host computer of the job completion.
The host computer reads the contents of responses based on the predetermined jobs completed by the local processors when all of the slave processors generate the interrupt signals.
The notifying unit has an AND gate, to which the interrupt signals generated by the slave processors are input. The notifying unit then notifies the host computer based on the output of the AND gate.
According to the second aspect of the present invention, a transmission method for transmitting a command in an electric part test system is provided. This electric part test system comprises a host computer which evaluates the test results of electric parts; a plurality of local processors, each of which is provided to each of the electric parts and receives each of the test results of the electric parts; a plurality of slave processors which notify the host computer of the test results received by the local processors; and common memories which the slave processors may write data to and the host computer may read the data from. In this electric part test system, the transmission method comprises a step in which the host computer writes the command to the common memories and a step in which the slave processors transfer the command from the common memories to the local processors.
According to the third aspect of the present invention, a transmission method of transmitting test results of electric parts in an electric part test system is provided. This electric part test system comprises a host computer which evaluates the test results; a plurality of local processors, each of which is provided to each of the electric parts and receives each of the test results of the electric parts; a plurality of slave processors, each of which is connected to the local processors by a common bus; and common memories which the slave processors may write data to and the host computer may read the data from. In this electric part test system, the transmission method comprises a step in which each of the slave processors judges whether the local processors connected to each of the slave processors receive the test results; a step in which the slave processors write the test results received by the local processors to the common memories; a step in which the slave processors generate interrupt signals to the host computer; and a step in which the test results written to the common memories are transmitted to the host computer when all of the slave processors generate interrupt signals.
This summary of the invention does not necessarily describe all necessary features. The invention may also be a sub-combination of these described features.